As a semiconductor device which complies with a recent trend in miniaturization of electrical devices, and which conforms with an automated assembly process, a chip size package (CSP) semiconductor device of a QFP (Quad Flat Package) type or a BGA (Ball Grid Array) type has been widely used.
These semiconductor devices require larger numbers of external connection terminals ever before as a result of faster and higher functioning signal processes of semiconductor element in the semiconductor device.
However, in the semiconductor device of a QFP type ("QFP type semiconductor device" hereinafter), it is difficult to increase the number of external connection terminals due to the fact that the external connection terminals are provided along the outer periphery of the external package.
On the other hand, in the semiconductor device of a BGA type ("BGA type semiconductor device" hereinafter), the number of external connection terminals can be increased more easily because the external connection terminals are provided two-dimensionally on the bottom surface of the package.
Thus, when it is required to increase the number of external connection terminals to realize faster and higher functioning signal processes on the semiconductor element, the BGA type semiconductor device is adopted.
Also, the BGA type semiconductor device has the package size which is reduced as small as possible to be close to the size (chip size) of the semiconductor chip so that it can be installed in a portable device as a small electrical device.
For example, Japanese Unexamined Patent Publication No. 121002/1997 (Tokukaihei 9-121002) (published date:May 6, 1997) discloses a semiconductor device as the BGA type semiconductor device wherein a semiconductor chip is connected to a wiring substrate by wire bonding with the surface of the semiconductor chip formed with MOS transistors, etc., facing upward, and the semiconductor chip is conducted to the external connection terminals via a wiring pattern of the wiring substrate.
The above BGA type semiconductor device has the structure, as shown in FIG. 11, in which a semiconductor chip 22 is bonded with a wiring substrate 21 by an adhesive paste 35, and the wiring substrate 21 and the semiconductor chip 22 are connected to each other by a conductive wire 23, and resin sealing is made by a mold resin 24.
The wiring substrate 21 has an arrangement in which a wiring pattern 28 is formed on an insulating substrate 26, and an internal connection region 32 on the periphery of the wiring pattern 28 and the electrode pad 33 on the upper surface of the semiconductor chip 22 are connected to each other by the wire 23.
On the wiring of the wiring substrate 21 is formed a solder resist 27, except on the internal connection region 32.
The wiring pattern 28 has the pattern as shown in FIG. 12, and other than the internal connection region 32 as shown in FIG. 11, there is formed an external connection region 30 along the periphery of a through hole 29 formed on the insulating substrate 26.
As shown in FIG. 11, the external connection region 30 is connected to an external connection terminal 25 made of a solder ball via the through hole 29. As a result, wiring is made from the semiconductor chip 22 and the internal connection region 32 connected to each other by the wire 23, via the external connection region 30, to the external connection terminal 25 formed on the lower side of the wiring substrate 21.
In the BGA type semiconductor device, in order to connect the semiconductor chip 22 to the wiring substrate 21, the adhesive paste 35 is used as described above. In such a case, the connection is made by the method in which an appropriate amount of the adhesive paste 35 is dropped on the wiring substrate 21, and the semiconductor chip 22 is bonded with the wiring substrate 21 on which the adhesive paste 35 was applied.
However, in this method of dropping the adhesive paste 35 on the wiring substrate 21, the amount of drops is not constant and various problems are generated by the difference in amount of drops.
For example, when the amount of the adhesive paste 35 dropped is excessive, as shown in FIG. 11, there is a case where the adhesive paste 35 protrudes over the internal connection region 32 of the wiring pattern 28. This causes a problem that the internal connection region 32 and the semiconductor chip 22 cannot be appropriately connected by the wire 23 due to the fact that the internal connection region 32 cannot be sufficiently provided.
On the other hand, when the amount of the adhesive paste 35 dropped is deficient, the adhesive paste 35 cannot be spread over the entire lower surface of the semiconductor chip 22, and there arise a spacing between the semiconductor chip 22 and the wiring substrate 21. This causes a problem that the semiconductor chip 22 is easily peeled off from the wiring substrate 21.
In order to solve this problem induced by the varying amount of drops of the adhesive paste 35, a method using an adhesive film instead of adhesive paste has been available.
For example, Japanese Unexamined Patent Publication No. 263734/1997 (Tokukaihei 9-263734) (published date:Oct. 7, 1997) discloses a semiconductor device having a structure, as shown in FIG. 13, in which the semiconductor chip 22 and the wiring substrate 21 are bonded with each other by an adhesive film 31.
Incidentally, in general, the solder resist 27 is formed so as to cover the wiring pattern 28 on the insulating substrate 26, and for this reason the surface of the solder resist 27 is in the form of concave and convex portions.
Thus, when the adhesive film 31 is mounted on the solder resist 27, there arises a spacing between the solder resist 27 and the adhesive film 31.
Also, when mounting the semiconductor chip 22, because the adhesive film 31 on the wiring substrate 21 has been heated already, the adhesive film 31 mounted on the wiring substrate 21 is softened and flows down into the concave portion on the surface of the solder resist 27, and as a result the surface shape of the adhesive film 31 becomes the copy of the concave and convex portions on the surface of the solder resist 27. When the semiconductor chip 22 is bonded with the adhesive film 31 thus deformed, there arise a spacing 36 as shown in FIG. 13 between the semiconductor chip 22 and the adhesive film 31.
If the semiconductor chip 22 is to be bonded with the wiring substrate 21 using such an adhesive film 31, it is required to move the semiconductor chip 22 back and forth in a direction parallel to the surface of the wiring substrate 21 while pressing the semiconductor chip 22 against the wiring substrate 21 so that the lower surface of the semiconductor chip 22 completely contacts the adhesive film 31.
However, even when the semiconductor chip 22 is bonded with the wiring substrate 21 in this manner by pressing, the spacing 36 generated between the semiconductor chip 22 and the adhesive film 31 cannot be eliminated completely, and the spacing 36 remains as bubbles at the portion where bonding is made.
As a result, by the bubbles at the portion where bonding is made, when the BGA type semiconductor device having a chip size package, for example, as shown in FIG. 12, is to be made connected to a print substrate, etc., of a portable device, etc., by heating, the chip size package is cracked by heat, presenting a problem that the percent defective is increased in a reliability test after connection is made.
The bubbles are generated at the portion where bonding is made because, as described, the bonding surface of the semiconductor chip 22 with the wiring substrate 21 takes the form of the concave and convex portions of the solder resist 27 due to the fact that the wiring pattern 8 is formed on the insulating substrate 26 and the solder resist 27 is formed thereon.
Thus, by forming the wiring pattern 28 on the lower surface of the insulating substrate 26 on the other side of the bonding surface of the semiconductor chip 22 with the wiring substrate 21, the bonding surface of the semiconductor chip 22 becomes level, and no bubbles are generated by the bonding of the semiconductor chip 22 and the wiring substrate 21.
However, when the wiring pattern 28 is to be formed on the lower surface of the insulating substrate 26 on the other side of the bonding surface of the semiconductor chip 22 in the described manner, in order to connect the wiring pattern 28 and the semiconductor chip 22 by the wire 23, it is required to provide the internal connection region 32 on the upper surface of the insulating substrate 26, that is, on the bonding surface of the semiconductor chip 22.
For this reason, the wiring pattern 28 needs to be provided on the both sides of the insulating substrate 26, and it is required to provide a through hole for wiring the internal connection region 32 and the external connection region 30 of the wiring pattern 28. To realize this, it is required to take a unique measure for connecting the wiring on the both sides of the wiring substrate 21, and this makes the manufacturing steps of the semiconductor device complex and increases the cost associated with manufacturing the semiconductor device.